Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3679994
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a clock generating circuit whose consumption current is small and which can prevent through current from flowing.
SOLUTION: A device is constituted of a current source I1, Pch-MOS FET (MOS transistor) M11 to which a drain and a gate are connected to the current source I1, a charge/discharge circuit 20 inputting clock output which is fed back with the gate voltage of the MOS transistor M11, a capacitor C, the two input/two output inversion circuits 30, 40 and 50 of series connection, which are connected to the charge/discharge circuit 20 in series, and a two input/one output inversion circuit 60 connected to the two input/two output inversion circuit 50 in series. Clock output is supplied from the two input/one output inversion circuit 60.
More Like This:
Inventors:
Youichi Tokai
Application Number:
JP2000388867A
Publication Date:
August 03, 2005
Filing Date:
December 21, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K3/354; H03K17/16; H03K17/687; (IPC1-7): H03K3/354; H03K17/16; H03K17/687
Domestic Patent References:
| JP2000106521A | ||||
| JP6140884A | ||||
| JP61234365A | ||||
| JP7297653A |
Attorney, Agent or Firm:
Takehana Kikuo
Hiroshi Uji
Hiroshi Uji