Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3814385
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce current consumption without deteriorating the processing performance.
SOLUTION: For the voltage level of back gate voltages VGP and VGN supplied to the back gate of MOS transistors P1, P2, N1 and N2 provided in an internal circuit 1, a voltage specified by selection signals among voltage generation circuits 2a, 2b, 4a and 4b for generating the voltages of the plural different voltage levels is selected, corresponding to the selection signals SELp and SELn corresponding to an operation mode from a mode detection circuit 10. The threshold voltage and drive current amount of the MOS transistor are adjusted, corresponding to the operation mode, and this semiconductor integrated circuit device operated at a high speed with the low current consumption is realized.
Inventors:
Eiichi Teraoka
Toyohiko Yoshida
Toyohiko Yoshida
Application Number:
JP28038897A
Publication Date:
August 30, 2006
Filing Date:
October 14, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L29/78; G11C11/408; H03F1/02; H01L21/822; H01L21/8238; H01L27/04; H01L27/092; H03K19/00; H03K19/094; (IPC1-7): H03F1/02; H01L21/8238; H01L27/092; H01L29/78; H03K19/094
Domestic Patent References:
| JP6291267A | ||||
| JP5347550A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai