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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0230113
Kind Code:
A
Abstract:

PURPOSE: To enable the alignment to be made normally in a lithographic process to form a wiring to be connected to a conductive layer by a method wherein an alignment mark is formed using a recession provided in the second insulating layer covering the conductive layer and a first insulating layer.

CONSTITUTION: In the title semiconductor integrated circuit device composed of a conductive layer 5, the first insulating film 2 adjacent to the conductive layer 5, the second insulating layer 7 covering the conductive layer 5 and the first insulating layer 2, a contact hole C provided on the part corresponding to the conductive layer 5 out of the second insulating layer 7 and an alignment mark M, the alignment mark M is constituted at least of a recession provided in the second insulating layer 7. For example, the interlayer insulating film 7 is etched away by RIE process to form a contact hole C on the diffused layer 5 simultaneously the alignment mark M is formed on the insulating film 2. Finally, the selective CVD of W is performed by reduction-reacting WF6 to selectively deposit W only inside the contact hole C to form an Al wiring 10 later.


Inventors:
TAKEDA MINORU
Application Number:
JP18055688A
Publication Date:
January 31, 1990
Filing Date:
July 20, 1988
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L21/3205; H01L21/027; H01L21/30; (IPC1-7): H01L21/027; H01L21/30; H01L21/3205; H01L21/88
Attorney, Agent or Firm:
Masatomo Sugiura



 
Next Patent: JPH0230114