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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0278266
Kind Code:
A
Abstract:

PURPOSE: To improve a self-refreshing timer circuit in accuracy by a method wherein silicon films, which form electrodes on one side of a resistor and a capacitor provided to the timer circuit, are formed to be substantially equal to each other in width.

CONSTITUTION: A self-refreshing timer built-in semiconductor integrated circuit is composed of a p--type semiconductor substrate 1. A resistor R is formed of a conductive film 4 on an insulating film 2 deposited on the primary face of the substrate 1, and a capacitor C is composed of a MIS capacitor formed by laminating an insulating film 3 and a conductive film 4 successively on the substrate 1. An n+-type semiconductor region 5 is provided to the primary face of the substrate 1 at the side wall of the conductive film 4, which has substantially the same structure as a MISFETQ. The conductive film 4 of the capacitor C is formed in the same manufacturing process that the conductive film 4 of the resistor R, and the films 4 are equal to each other in width W. The length L of the conductive films 4 of the capacitor C and the resistor R are large as compared with the width W, and the value of the resistor R and the capacitor C are inversely and directly proportional to the width W respectively. The period of the timer is directly proportional to CR, so that the width W errors are compensated with each other and the timer is improved in accuracy.


Inventors:
KUBONO SHIYOUJI
Application Number:
JP22879188A
Publication Date:
March 19, 1990
Filing Date:
September 14, 1988
Export Citation:
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Assignee:
HITACHI LTD
HITACHI VLSI ENG
International Classes:
G11C11/406; G11C11/407; H01L21/822; H01L21/8244; H01L27/04; H01L27/11; (IPC1-7): G11C11/407; H01L27/04; H01L27/11
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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