Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0575425
Kind Code:
A
Abstract:
PURPOSE: To prevent mis-reading of an input signal due to fluctuation of a voltage level of an internal power supply line by suppressing a fluctuation of a voltage level of an internal power supply line at pull-up and pull-down.
CONSTITUTION: A pull-up circuit is formed by connecting a pMOS 26 whose threshold voltage is Vth26 and a pMOS 27 whose threshold voltage is Vth27 (>Vth26) in parallel and in which on/off of the pMOS 26, 27 is controlled by a pMOS control signal SP, and a pull-down circuit is formed by connecting an nMOS 28 whose threshold voltage is Vth28 and an nMOS 29 whose threshold voltage is Vth29 (>Vth28) in parallel and in which on/off of the pMOS 28, 29 is controlled by an nMOS control signal SN.
Inventors:
IKUTA NOBUO
NAKAYAMA TOSHIHIRO
MIYASHITA TOYOKO
NAKAYAMA TOSHIHIRO
MIYASHITA TOYOKO
Application Number:
JP23053791A
Publication Date:
March 26, 1993
Filing Date:
September 10, 1991
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03K17/16; G11C11/409; H03K17/687; H03K19/0175; (IPC1-7): H03K17/16; H03K17/687; H03K19/0175
Attorney, Agent or Firm:
Teiichi
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