PURPOSE: To reduce the defects accompanying making integration and efficiency of a semiconductor integrated circuit device higher by producing dielectric breakdown in the memory cell having a capacitor connected in series to the MOSFET for address selection at the time of writing and sensing the memory by impressing a voltage different from the precharge onto the common electrode of the capacitor at the time of reading.
CONSTITUTION: One word line is selected by decoding the signal taken into a buffer X-AB in synchronization with the line address strobe signal from a CPU, and a data line is selected for a signal CAS. The memory array is constituted from a normal circuit, a redundancy circuit R-ARY1 which remedies the defect in the unit of data line DL and a R-ARY2 which remedies the defect in the bit unit, and a sense amplifier SA1 corresponding to the memory array conducts re-writing to the memory cell. Input/output lines included in the decoder Y-DEC and R-YED are selectively connected with the data lines in the memory cell array through a line SW and also to the I/O through a selection circuit SELECT. This constitution can incorporate a PROM having high integration of the same size as the D-type memory cell.
KAJITANI KAZUHIKO
NAKAMURA MASAYUKI
KITSUKAWA GORO
KAWAHARA TAKAYUKI
IWAI HIDETOSHI
