To set a test mode state by utilizing a reset terminal and other input terminals, without adding test-only terminals in a semiconductor integrated circuit device which has the reset terminal and another input and does not use the other input signal when being reset.

A test mode is set such that when a reset terminal 2 is set to state 1, a reset signal for a test mode setting circuit goes to state 1, a test mode setting circuit 3 is released from a reset state, a reset signal 6 for a circuit under test goes to state 0, and a circuit under test 7 goes to a reset state. While the reset terminal 2 is in state 1, a train of clock pulses are applied to the input terminal 1 for a fixed time and a test mode signal outputted from the test mode setting circuit 3 goes state 1. At the same time the reset signal 6 for the circuit under test goes to state 1, and then the circuit 7 under test is released from the reset state and goes to a test mode state.