Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS58182242
Kind Code:
A
Abstract:
PURPOSE:To realize speed-up of processing by shortening wiring length and reducing capacitance and by separating fixed wirings in the course of processing and embedding them in the MOS type master slice system of three-level wirings. CONSTITUTION:The 2-input basic cells 7 of the CMOS type master slice system IC form array 5. The P<+> layer 8, N<+> layer 9 and a poly-Si gate wiring form the P-channel and N-channel FET's. The separated fixed wiring 10 of poly-Si is embedded in the same way as each array on the extension line of the gate wiring 6. The fixed wirings 6, 10 are common for all IC's and only when region of wiring 6 is full and not available in the 2-level metal wirings in individual wirings, a through hole is provided and thereby the fixed wiring 10 and metal wiring are connected. According to this structure, wiring length can be shortened, wiring capacitance can be reduced and high speed operation can also be realized.
Inventors:
YAMADA SUKETAKA
Application Number:
JP6502182A
Publication Date:
October 25, 1983
Filing Date:
April 19, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/3205; H01L21/82; H01L23/52; H01L27/04; H01L27/118; (IPC1-7): H01L21/88; H01L27/04
Domestic Patent References:
| JPS5621364A | 1981-02-27 |
Attorney, Agent or Firm:
Uchihara Shin