Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS60211959
Kind Code:
A
Abstract:
PURPOSE:To enable to use selectively the same memory area as an AND array or an OR array by a method wherein a memory element, which is actuated by receiving the signal of the input conductor disposed in a matrix form, and a memory element, which is actuated by receiving the signal of the output conductor disposed in a matrix form, are selectively provided at the intersecting point of the input conductor and the output conductor utilizing the write-in system of the memory information thereof. CONSTITUTION:A signal of the same phase as that of an input signal and an anti- complementary signal to the input signal are formed in an input circuit IN and a complementary signal, which is fed to the next memory array, is formed. An AND array AND and an OR array OR are disposed on the memory array, and besides, an AND/OR array AND/OR, which can be used in common by changing-over selectively to the AND array AND or the OR array OR, is disposed in the boundary part of both arrays AND and OR. Accordingly, an input circuit IN', which is actuated selectively, has been prepared in a part of the input circuit IN, where corresponds to this AND/OR array AND/OR, and an output circuit OUT', which is actuated selectively, has been prepared in a part of an output circuit OUT, where corresponds to the AND/OR array AND/OR, as well.
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Inventors:
MASUDA KOUJI
Application Number:
JP6768984A
Publication Date:
October 24, 1985
Filing Date:
April 06, 1984
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L27/10; H01L21/82; H01L27/112; H03K19/177; (IPC1-7): H01L27/10; H03K19/08
Attorney, Agent or Firm:
Akio Takahashi
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