PURPOSE: To facilitate the function test of a RAM at an optimum test frequency by assigning an output terminal of a frequency divider to an input terminal of the RAM at function test so as to add a few pins and circuits.

CONSTITUTION: A mode signal selects the A position information of selectors 4, 5 at test to reset a frequency divider 3, a signal Q8 brings a RAM1 into the write mode and signals Q0WQ7 write information (0)N in an address (00)N by using the signal Q9. '0' is written in all bits of a write RAM of an address added by each clock. The frequency divider output is (100)H by succeeding clocks and the signal Q8 brings the RAM to the read mode and the address to (00)H, which is compared with '0' of the signal Q9. If normal, a signal Y of the 8EXNOR 6 goes to '1' and a NAND gate 7 outputs '0'. Until the frequency divider output is (OFF)H, it is repeated to complete the storage test of all bit '0'. Similarly, the operation above is repeated until the frequency divider output is (2FF)H, (3FF)H to complete the function test of '1', '0'. Through the constitution above, the test program is facilitated and the test time is reduced.