PURPOSE: To attain a high speed operation by inputting the output of a logic circuit receiving plural input signals and outputting the result of AND operation in response to a clock to an OR circuit in response to the clock via a delay circuit.

CONSTITUTION: A 1st logic circuit 1 has plural transistors (not shown) connected in parallel and receiving plural input signals Si respectively, and outputs the AND operation result Sm of the input signal Si in response to a change in the prescribed level of a clock CK. The result Sm is fed to a 2nd logic circuit 2 together with an output from other delay circuit (not shown) via a delay circuit 3. The 2nd logic circuit 2 outputs the result So of OR operation to plural input signals Sm in response to the prescribed level change of the clock CK similarly. Thus, high speed logic operation is attained.