To provide a semiconductor integrated circuit device capable of shortening a test time.

When testing this semiconductor integrated circuit device, following processes are executed, namely: a selection process wherein a multiplexer 19 selects the first observation object signal from observation object signals P1-P4; a clock supply process wherein a clock supply circuit 27 supplies a clock satisfying a setup hold restriction to delay fluctuation of the observation object signal outputted from the multiplexer 19 to a flip-flop 26; a taking process wherein the flip-flop 26 takes the observation object signal outputted from the multiplexer 19, synchronously with a clock outputted from the clock supply circuit 27; and a delay adjustment process wherein a delay adjustment circuit 28 inputs the observation object signal outputted from the flip-flop 26, adjusts delay thereof, and can sample the observation object signals P1-P4 at a common timing at an output end thereof.

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