Title:
SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD OF CONTROLLING STRESS IMPRESSION AMOUNT ONTO SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JP2004226220
Kind Code:
A
Abstract:
To freely control a stress impression amount and impression timing for each block.
Electric power source switches 201, 202, 203 are provided respectively in circuit blocks 101, 102, 103, the electric power source switches are respectively controlled individually during burn-in inspection to regulate electric power source supply times, i.e. stress amounts, to the respective blocks. The stress of required enough amount is impressed to the circuit block requiring the longest stress impression time, and an excess stress is prevented from being impressed to the other circuit blocks, by this manner.
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Inventors:
KAWANO TAKESHI
Application Number:
JP2003013991A
Publication Date:
August 12, 2004
Filing Date:
January 22, 2003
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/30; H01L21/822; H01L27/04; G01R31/26; (IPC1-7): G01R31/30; G01R31/26; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Kenichi Hayase
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