To provide a semiconductor integrated circuit capable of preventing breach of timing and being highly integrated without increasing designing TAT and its designing method.

Timing analysis of a net list is performed at the time of logical synthesis and when breach of holding time is detected in a path between FF circuits 11, 12, the FF circuit 12 at a rear stage is replaced with an FF circuit 30 for correction. The FF circuit 30 for correction is provided with a circuit structure in which a delay cell 31 is inserted into the input stage and a delay cell 32 is inserted into the output stage. In addition, the delay quantity of the delay cell 32 is set so as to become smaller than that of the delay cell 31. Thus, the input time of data to the FF circuits is delayed by embedding the delay cell 31 in the input stage and the output time of data to the FF circuit 30 for correction is delayed by embedding the delay cell 32 in the output stage.