To provide a design method for a semiconductor integrated circuit etc., that can prevent a flip-flop from becoming difficult to operate normally.
This device is equipped with a net list recording part 4, a cell library recording part 5, a wiring delay predicted value recording part 6, a hold time calculation part 7 which calculates a hold time as a designed sue value of a flip-flop, a hold time maximum value extraction part 8 which extracts a maximum value among hold times as designed use values, a hold time maximum value conversion part 9 which converts the maximum value among the hold times as the designed use values into a clock skew, a cell arrangement part 10, a clock tree synthesis part 11, a wiring part 12, a timing simulation part 13 which performs timing simulation, and a timing simulation result check part 14 which arranges wires and makes the timing simulation part perform timing simulation again in case of a timing error.
Fujitsuna Hideyoshi
Osamu Suzawa
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