To prevent a clock skew of a plurality of scan flip-flop groups.

A fresh clock terminal 11 is set at one input terminal of a data selector 7, so that a B group is provided with a fresh path through which system clocks are input from the clock terminal 11 via the data selector 7 and a clock tree driver 4B. When a full scan is to be inserted in a sequential circuit 40, a test mode is set to '1' by the data selector 7, and the system clock is input to an A group from a system clock terminal 1 via a clock tree driver 4A while the system clock is input to the B group from the test clock terminal 11 via the clock tree driver 4B. The full scan is inserted by a full scan CAD tool under different clock systems between the A and B groups.