To reduce characteristic variations of a PLL circuit due to variations in element size of transistors and reduce increase in circuit scale and power consumption when employing an on-chip loop filter.

A semiconductor integrated circuit incorporates a phase-locked loop circuit comprising a phase/frequency comparator 1, a loop attenuator 2, a charge pump 3, a loop filter 4, a voltage-controlled oscillator 5 and a frequency divider 6. The attenuator 2 includes a sampling circuit 21 and a counter 22. A sampling pulse SPL_CLK and first and second output signals output from the phase/frequency comparator 1 are supplied to the circuit 21, which in turn outputs a sampling output signal. When completing counting up a predetermined number of sampling pulses output from the circuit 21, the counter 22 outputs a count completion output signal. The charge pump 3 outputs a charge current or discharge current to the loop filter 4 in response to the count completion output signal.