To improve the trackability to frequency variation of a sampling clock signal at an input side.

An asynchronous-type sampling rate converter 1 comprises: a converting circuit 11; and a conversion-ratio calculation circuit 12, and the circuit 11 generates an output signal by rate conversion of a digital input signal. An input/output-rate-ratio detection circuit 121 of the calculation circuit 12 determines a rate conversion ratio according to a ratio of frequencies of sampling clocks at an input side and an output side. A rate-ratio processing circuit 122 of the circuit 12 comprises a plurality of LPF processing circuits 1221 and 1222 having different cut-off frequencies, and a selection circuit 124 of the circuit 12 selects any of an output signal among a plurality of output signals in response to the difference between the output signals of the plurality of LPF processing circuits and then outputs the output signal. If the difference is small, the selection circuit 124 selects the output signal from the LPF processing circuit having a low cut-off frequency, whereas if the difference is large, the selection circuit 124 selects the output signal from the LPF processing circuit having a high cut-off frequency.