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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT TEST DEVICE AND METHOD
Document Type and Number:
Japanese Patent JP2003196999
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit test device and a method which can obtain a test result of a memory to be tested, having automatic operating functions of a flash memory or the like for sorting each test item.

The device is a semiconductor integrated circuit test device for performing a text of a memory 20 to be tested in which automatic operating functions for performing a plurality of times of change operation for changing stored contents inside are provided. The device is provided with a memory 15 furnished with a plurality of storage regions in which test results for the automatic operating functions of the memory 20 to be tested are stored, and a storage region for storing a test result is switched in accordance with a test item of a test for the automatic operating functions of the memory 20 to be tested.


Inventors:
KAWARASAKI FUTOSHI
Application Number:
JP2001392988A
Publication Date:
July 11, 2003
Filing Date:
December 26, 2001
Export Citation:
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Assignee:
ANDO ELECTRIC
International Classes:
G11C16/02; G11C17/00; G11C29/00; G11C29/56; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; G11C16/02; G11C17/00
Attorney, Agent or Firm:
Masatake Shiga (6 people outside)