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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT WITH BYPASS CIRCUIT BUILT THEREIN
Document Type and Number:
Japanese Patent JPH04282913
Kind Code:
A
Abstract:

PURPOSE: To facilitate a complicated test in terms of a board level by integrating a bypass circuit even to a high speed operation circuit because a delay in a signal by a selector is not necessary to be taken into account.

CONSTITUTION: Upon the receipt of a test mode switching signal from an input section 10, mode changeover switches 2, 3 are conductive, the normal mode is switched into the test mode, and an output terminal 5 of an output buffer 7 and an output terminal 4 of an input buffer 6 are connected via a bypass circuit 1. Moreover, the output buffer 7 receives an output high impedance switching signal from an input section 11 in this case and the impedance reaches a high impedance. Since the output terminal 5 of the output buffer 7 and the output terminal 4 of the input buffer 6 are connected via the changeover switches 2, 3 in this way, the signal is bypassed at a high speed.


Inventors:
YANODA MASASHI
Application Number:
JP7046191A
Publication Date:
October 08, 1992
Filing Date:
March 12, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/66; H01L21/822; H01L27/04; H03K17/00; (IPC1-7): H01L21/66; H01L27/04; H03K17/00
Attorney, Agent or Firm:
Yoshiyuki Iwasa



 
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