Title:
バラクタデバイスを備えた半導体集積回路
Document Type and Number:
Japanese Patent JP3549479
Kind Code:
B2
Abstract:
A CMOS line driver is made up of p- and nMOS transistors. A pMOS varactor is interposed between the source of the pMOS transistor and a power supply, while an nMOS varactor is interposed between the source of the nMOS transistor and ground. The sizes of each of these MOS varactors may be the same as those of the p- or nMOS transistor. Alternatively, each of these MOS varactors may have a channel area twice greater than that of the p- or nMOS transistor. The inverted version of a signal input to the line driver is supplied to the gates of the MOS varactors. In this manner, the MOS transistors, making up the line driver, can switch at a high speed.
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Inventors:
Kanji Otsuka
Yasushi Usami
Yasushi Usami
Application Number:
JP2000315360A
Publication Date:
August 04, 2004
Filing Date:
October 16, 2000
Export Citation:
Assignee:
大塚 寛治
宇佐美 保
松下電器産業株式会社
沖電気工業株式会社
三洋電機株式会社
シャープ株式会社
ソニー株式会社
株式会社東芝
日本電気株式会社
株式会社ルネサステクノロジ
富士通株式会社
三菱電機株式会社
ローム株式会社
宇佐美 保
松下電器産業株式会社
沖電気工業株式会社
三洋電機株式会社
シャープ株式会社
ソニー株式会社
株式会社東芝
日本電気株式会社
株式会社ルネサステクノロジ
富士通株式会社
三菱電機株式会社
ローム株式会社
International Classes:
H01L27/04; H01L21/822; H01L21/8222; H01L21/8236; H01L27/06; H01L27/088; H03K19/017; (IPC1-7): H01L21/822; H01L21/8222; H01L21/8236; H01L27/04; H01L27/06; H01L27/088
Domestic Patent References:
| JP2000196018A | ||||
| JP2000036561A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita
Yamato Tsutsui
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita
Yamato Tsutsui