Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2002109881
Kind Code:
A
Abstract:
To perform data transfer always with constant latency against variations in operating frequency, read time, etc.
A clock asynchronous type circuit 1 performs data read operation according to a read control signal READ. Read data RD are read out of the clock asynchronous circuit 1 a certain delay time td latter. The read data RD are latched in one latch circuit selected out of N latch circuits (R1, R2...RN) 3. The latch circuit is selected according to not a clock signal Clock, but a control signal RLPLS. The control signal RLPLS is a signal indicating that the read data RD are outputted from the clock asynchronous circuit 1, so the latch circuit is selected always after the read data RD are outputted.
Inventors:
KOUCHI TOSHIYUKI
YOSHIHARA MASAHIRO
KOINUMA HIROYUKI
YOSHIHARA MASAHIRO
KOINUMA HIROYUKI
Application Number:
JP2000297705A
Publication Date:
April 12, 2002
Filing Date:
September 28, 2000
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F12/00; G11C7/10; G11C7/22; G11C11/413; G11C8/18; G11C11/407; (IPC1-7): G11C11/407; G06F12/00; G11C11/413
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)
Previous Patent: MULTIPORT MEMORY DEVICE
Next Patent: RESET DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR STORAGE DEVICE
Next Patent: RESET DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR STORAGE DEVICE