Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3161387
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that reduces the number of elements and a circuit area, while stably supplying a bias voltage and at the same time can fully suppress the propagation of noise for a higher frequency noise than the response speed of a bias circuit.
SOLUTION: A semiconductor integrated circuit 1 is provided with a first current source M1, connected to first power supplies AVDD and AVSS and a second current source M2 connected to second power supplies DVDD and DVSS. The semiconductor integrated circuit is further provided with a bias circuit BS1, that is connected to the first power supply AVDD and directly supplies a bias voltage VG1 to a first current source M1 and supplies it to the second current source M2, via a filter F1.
Inventors:
Masafumi Mitsuishi
Application Number:
JP29557097A
Publication Date:
April 25, 2001
Filing Date:
October 28, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L27/04; H01L21/822; (IPC1-7): H01L27/04; H01L21/822
Domestic Patent References:
| JP61114608A | ||||
| JP6441307A |
Attorney, Agent or Firm:
Kiyoshi Inagaki