Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3924107
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To read out data stored in a memory cell at high speed in a semiconductor memory having a memory cell.
SOLUTION: This device is provided with plural data lines, a sense amplifier, and a dummy data line. The data lines are arranged adjacently one another, and transmit data read out from a memory cell. The sense amplifier receives data, and outputs an amplified signal. The dummy data line is arranged along the outside of a data bus line consisting of data lines. The dummy data line performs voltage variation being same as voltage of the data line at the time of read-out operation of data stored in the memory cell. Therefore. accumulated quantity of electric charges for parasitic capacity formed between the data line and the dummy data line at the time of read-out is the minimum. Consequently, variance of rise time of plural data lines is made small, and a read-out time (access time) is shortened.
Inventors:
Yasushi Kasa
Application Number:
JP2000064580A
Publication Date:
June 06, 2007
Filing Date:
March 09, 2000
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C16/06; G11C7/02; G11C7/10; G11C7/14; (IPC1-7): G11C16/06
Domestic Patent References:
| JP4252494A | ||||
| JP5151776A | ||||
| JP64008579A |
Attorney, Agent or Firm:
Furuya Fumio
Eisuke Suzuki
Eisuke Suzuki