Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3944298
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for controlling the output resistance of an output buffer circuit as prescribed at all times without lowering data transmission quality.
SOLUTION: The D latches 60-63 and 65-68 of the latch circuit parts 16 and 17 of an output resistance control output buffer circuit 2 receive output resistance control trigger signals STRB in T input in common, pull-up bit control signals U0-U3 are received in the D input of the D latches 60-63 and pull- down bit control signals D0-D3 are received in the D input of the D latches 65-68. The output resistance of transistors QU0-QU3 and the transistors QD0-QD3 is controlled by respective data latched in the latch circuit parts 16 and 17. The output resistance control trigger signals STRB are the signals to be 'H' sufficiently after an output resistance control signal decision period decided by the pull-down bit control signals D0-D3 and the pull-down bit control signals U0-U3.
Inventors:
Mitsuo Shinkin
Ishii
Katsushi Asahina
Ishii
Katsushi Asahina
Application Number:
JP3282998A
Publication Date:
July 11, 2007
Filing Date:
February 16, 1998
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H03K19/0175; H03K19/00; (IPC1-7): H03K19/0175
Domestic Patent References:
| JP7036580A | ||||
| JP8340245A | ||||
| JP4321320A | ||||
| JP6164361A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita
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