Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP6697798
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of performing an actual operation test of a data path from a sequential circuit that operates on the basis of a clock before frequency division to a sequential circuit that operates on the basis of a clock after frequency division.SOLUTION: A semiconductor integrated circuit 1 comprises: a frequency divider 13 that operates in at least any one of a first mode and a second mode; and a control circuit 12 that controls the frequency divider 13 so that the frequency divider 13 operates in any one of the first mode and the second mode. The frequency divider 13, in the first mode, divides an inputted first clock by a predetermined division number via a second path including a first path to generate and output a second clock, and in the second mode, outputs the first clock as the second clock via the first path.SELECTED DRAWING: Figure 1
Inventors:
Tatsuya Hino
Application Number:
JP2015209926A
Publication Date:
May 27, 2020
Filing Date:
October 26, 2015
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
G01R31/28; H03K19/096; G01R31/3185; H03K21/00; H03K21/40
Domestic Patent References:
| JP10233679A | ||||
| JP56093434A | ||||
| JP11174123A | ||||
| JP2011257240A | ||||
| JP2012057997A |
Attorney, Agent or Firm:
Hide Tanaka Tetsu
Hideaki Shioya
Hideaki Shioya