PURPOSE: To arrange a memory cell on 2/3 of the intersected points of word lines and bit lines and to improve the degree of integration by shaping bit lines to be reference voltages on two sense-amplifiers.

CONSTITUTION: The basic unit of a memory cell array A is constituted of ward lines 1 to 3 and bit lines 4 to 6 intersecting them, the memory cells are not present on the intersected points of the lines 1 and 4, 2 and 5 and 3 and 6, but the memory cells are present on the intersected points of the residual word ane bit lines. Sence-amplifiers 7 and 8 are present on both sides of the array A, the line 4 is connected to the amplifier 7 via TG 9, the lines 5 and 6 are connected together via TG 10 and TG 11 respectively and they are connected to the amplifier 7. Also, the line 4 is connected via TG 9, the cell array and TG 12 and the lines 5 via TG 10, the cell array and TG 13 are connected together and they are connected to the amplifier 8. The line 6 is connected to the amplifier 8 via TG 14. Thus, the bit lines 4 to 6 are shared on the sence- amplifiers 7 and 8.