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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH07106520
Kind Code:
A
Abstract:

PURPOSE: To reduce the electric field of a gate after input of a voltage even when a voltage higher than a normal rating is inputted by a method wherein an input terminal circuit having an n type transistor with the substrate potential fixed to the ground potential is provided.

CONSTITUTION: An input terminal circuit has an n type transistor 2 with the substrate potential fixed to the ground potential, and the transistor 2 is inserted in series between an external terminal 5 and the input terminal circuit. By preparing the substrate potential of the input terminal circuit independently of the substrate potential of other circuits, electric field induced between the gate electrodes 7 of transistors 1 and 2 and a p type well 13 can be relaxed even when an input signal higher than an initial rating is inputted. In short, by fixing the substrate potential of the n type transistor 2 within the input terminal circuit to which a high electric field is applied to the potential of the ground electrode, Vss, it is possible to reduce the electric field.


Inventors:
NAGASE KOICHI
Application Number:
JP24533993A
Publication Date:
April 21, 1995
Filing Date:
September 30, 1993
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/04; G11C11/407; G11C11/408; G11C11/409; H01L21/822; H03K19/003; H03K19/0948; (IPC1-7): H01L27/04; H01L21/822; H03K19/003; H03K19/0948
Attorney, Agent or Firm:
Soga Doteru (6 people outside)