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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH08298292
Kind Code:
A
Abstract:

PURPOSE: To provide a semiconductor integrated circuit capable of reducing a chip area of an internal circuit forming region and preventing a latch-up phenomenon in the internal circuit forming region.

CONSTITUTION: A flow of substrate current to the internal circuit from an diffusion element connected to an input terminal or output terminal can be interrupted by forming a diffusion element to be connected to an output terminal or an input terminal at the side (region 2) coming into contact with a region 1 where an input terminal or output terminal is formed, and also forming diffusion elements except the diffusion element formed in the region 2 at the side (region 3) coming into contact with the internal circuit forming region 4 among the diffusion elements constituting the input circuit or output circuit.


Inventors:
MEN KIYOSHI
OTANI KAZUHIRO
Application Number:
JP15396596A
Publication Date:
November 12, 1996
Filing Date:
June 14, 1996
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/8238; H01L27/08; H01L27/092; (IPC1-7): H01L21/8238; H01L27/08; H01L27/092
Domestic Patent References:
JPS6151958A1986-03-14
JPS6132562A1986-02-15
JPS5788774A1982-06-02
Attorney, Agent or Firm:
Tomoyuki Takimoto (1 person outside)