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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS56118373
Kind Code:
A
Abstract:

PURPOSE: To improve stability and precision of a circuit of an IC memory with floating gate type N channel FAMOS, by controlling in a proper way the writing time comparing some of the voltage of the input line to the input voltage.

CONSTITUTION: 35, 361...36N are MOS devices and 371∼37N are n channel FAMOS devices. As the threshold voltage VTH increases because of the writing in the device 37, so the electric differential V38 increases at the point 38. Therefore comparing the V38 and the signals from D/A converting part 31, the input is suspended to turn the FET35 off when the change of the V38 (VTH) reaches the desired value. With such an arrangement, the scattering in the input to the device 37 is completely prevented, so that the operations with high precision and high resolution can be achieved.


Inventors:
NAKASAKI YASUTAKA
Application Number:
JP2240780A
Publication Date:
September 17, 1981
Filing Date:
February 25, 1980
Export Citation:
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Assignee:
SUWA SEIKOSHA KK
International Classes:
H03M1/00; G11C16/04; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C27/00; H01L29/78; H03K13/02



 
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