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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5658194
Kind Code:
A
Abstract:

PURPOSE: To prevent the malfunction and breakdown caused by the abnormal voltage applied to the input terminal for the semiconductor memory circuit which performs the writing of information and others with application of high voltage, by installing the switching circuit which forms a discharge path to the input terminal.

CONSTITUTION: The driving transistor T2 which is driven by the signal supplied from the writing terminal PR which supplies the half-selective writing voltage in the writing mode via the semiconductor IC such as the field programmable read-only memory or the like, the load transistor T1 and the leak transistor T3 which forms a discharge path are connected between the row line Wj and the basement gate terminal SUB. The transistor T3 is kept on unless the half-selective writing voltage is supplied to the terminal PR even though the writing voltage higher than the threshold level may arrive at the line Wj, and thus only the line Wj has never increase of the potential by the effect of the electrostatic field owing to the earthing of the line Wj.


Inventors:
WADA TOSHIO
Application Number:
JP8022380A
Publication Date:
May 21, 1981
Filing Date:
June 16, 1980
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/417; G11C5/14; G11C16/06; G11C17/00; H01L23/62; H03K17/08; (IPC1-7): G11C11/34; G11C11/40; H01L23/56; H03K17/00



 
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