Title:
通信用半導体集積回路および無線通信システム
Document Type and Number:
Japanese Patent JP3997525
Kind Code:
B2
Abstract:
A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit for the transmission PLL circuit is configured to be operable in a plurality of bands. The communication semiconductor integrated circuit also comprises a circuit for measuring the oscillating frequency of the oscillator circuit for the transmission PLL circuit, and a storage circuit for storing the result of measurement made by the measuring circuit. A band to be used by the oscillator circuit for the transmission PLL circuit is determined based on values for setting the oscillating frequencies of the oscillator circuit forming part of the reception PLL circuit and the intermediate frequency oscillator circuit, and the result of measurement stored in the storage circuit.
Inventors:
Jiro Shinbo
Hirotaka Osawa
Noriyuki Kurakami
Masumi Kasahara
Robert Astor Henschau
Hirotaka Osawa
Noriyuki Kurakami
Masumi Kasahara
Robert Astor Henschau
Application Number:
JP2003049135A
Publication Date:
October 24, 2007
Filing Date:
February 26, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
Teepee com limited
Teepee com limited
International Classes:
H04B1/40; H03D3/00; H03J1/00; H03L7/089; H03L7/099; H03L7/10; H03L7/18; H03L7/187; H03L7/193; H04L27/00; H03B1/00; H03B5/12
Domestic Patent References:
| JP10271001A | ||||
| JP2001251186A | ||||
| JP11340820A | ||||
| JP2000091941A | ||||
| JP2003318732A |
Attorney, Agent or Firm:
Shizuyo Tamamura
Tomio Dainichi
Tomio Dainichi