半導体集積回路、電子機器及び移動体

Title:

半導体集積回路、電子機器及び移動体

Document Type and Number:

Japanese Patent JP7211010

Kind Code:

B2

Abstract:

A semiconductor integrated circuit includes a first MOS transistor, a second MOS transistor, and a P+ region. The first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which a first power supply voltage is supplied to the first N-type region. The second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which a second power supply voltage higher than the first power supply voltage is supplied to the third N-type region. The P+ region is supplied with the first power supply voltage. In plan view of the semiconductor substrate, the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and the P+ region is located between the first N-type region and the third N-type region.

More Like This:

JPH08306800	PROTECTIVE DEVICE FOR INTEGRATED CIRCUIT
JPS6489445	WIRING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
JP4807768	Power transistor device and power control system using it

Inventors:

Noboru Itomi

Application Number:

JP2018205039A

Publication Date:

January 24, 2023

Filing Date:

October 31, 2018

Export Citation:

Click for automatic bibliography generation Help

Assignee:

Seiko Epson Corporation

International Classes:

H01L21/822; H01L21/82; H01L27/04

Domestic Patent References:

JP2002209375A
JP2003279A
JP3083375A
JP2002280460A
JP2003197792A

Foreign References:

US20020135022

Attorney, Agent or Firm:

Satoshi Nakai
Hiroki Matsuoka
Masayuki Imamura

Previous Patent: Sound insulation structure for internal combustion engines

Next Patent: METHOD FOR FORMATTING DISC MEMORY DEVICE