PURPOSE: To easily and inexpensively manufacture a device and to drive it with low power consumption, by providing a data input counter circuit, a data completion counter circuit where data input is completed, and a data output delay means, and delaying plural data output signal time for the data input.

CONSTITUTION: A counter circuit 25 fetches a data input signal D1 by a clock signal CPI, and outputs a data output signal Do via data output terminals 1B, 1C,∼1M, and holds the state. Next, when the data input signal D1 disappears, the counter circuit 25 is released from a reset state. The counter circuit 25 outputs the signal by the same number of clocks designated to a counter circuit 13, and it becomes the clock signal of a delay F/F circuit 14 via OR circuits 16, 17, and 18. A state where no data input signal D1 exists is fetched by the clock signal CPI, and the data output signals from the data output terminals 1B, 1C,∼1M also disappear.