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Title:
SEMICONDUCTOR INTEGRATING CIRCUIT
Document Type and Number:
Japanese Patent JPS62175015
Kind Code:
A
Abstract:

PURPOSE: To keep satisfactorily the balance of rise and fall waveforms and to minimize the leakage current between electric power source by connecting successively the division between respective power source terminals of the logic circuit from first step to an (n)-th step through at least one element for dropping the voltage to drop the power source voltage impressed to the power source terminal of the logic circuit of the (n)-th step.

CONSTITUTION: Between a VDD terminal 6 of the first inverter 1 and a VDD terminal 7 of the second step inverter 2, the (n) pieces of a diode 10 are serially connected in the normal direction to the electric power source voltage as the element for dropping the voltage. Between the VDD terminal 7 of the inverter 2 and a VDD terminal 8 of an inverter 3, the (m) pieces of the diode 10 are serially connected as the element for dropping the voltage. An power source terminal 9 is connected to the VDD terminal 8 of the third step inverter 3. The voltage of the VDD terminal of the second step inverter is lower only for the normal direction voltage drop of the (m) pieces of the diode 10 and the voltage of the VDD terminal 6 of the first step is further lower only for the (n) pieces of the diode, compared with the voltage of the VDD terminal 8 of the third step inverter.


Inventors:
MORIGAMI TAKASHI
Application Number:
JP5425486A
Publication Date:
July 31, 1987
Filing Date:
March 11, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K19/0185; H03K19/0948; (IPC1-7): H03K19/00
Domestic Patent References:
JPS58129830A1983-08-03
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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