PURPOSE: To decrease remarkably the number of signal connecting pints by providing two sets of serial/parallel converters loading serially data to the other converter while one converter receives data serially and using a couple of serial signals for the transmission/reception of signals between chips.

CONSTITUTION: When a selection signal 54 of a serial/parallel converter output selector 18 goes to a high level, the serial/parallel converter output selector 18 selects the output of the 2nd serial/parallel converter shift register 17 and data A2∼H2 are outputted to an inter-chip signal group 57. The serial/parallel converter output selector 18 consists of two AND gates and an OR gate, the output is added with a capacitor C and when the output is switched and the data of same level exists, no switching noise is generated. Through the procedure above, the serial output of an inter-chip signal output line 40 is outputted in parallel as the same data of the signal group 32 as an inter-chip signal group 57 continuously from a serial/parallel converter. Thus, no idle time of transfer exists and the inter-chip signal is transmitted and received efficiently.