Title:
SEMICONDUCTOR MANUFACTURING SYSTEM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3555859
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing system by which chip position information of assembly discriminated as a fault is read without removing resin of a package, the cause of fault is eliminated quickly, and the manufacturing yield of chips is improved quickly.
SOLUTION: A replacement address reading device 41 reads out a redundant address from a redundant circuit of a semiconductor device being defective in a test after sealing in a package. A chip position analyzing device 42 estimates a log number, wafer number, and a chip number of the semiconductor device being defective from combination of this redundant address. A fault distribution generating device 32 generates distribution of defective chips in each wafer in a log based on the obtained lot number, wafer number, and chip number. A fault cause estimating device 34 estimates a manufacturing device and a manufacturing process being the cause of fault in a wafer process based on this distribution.
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Inventors:
Sumio Ogawa
Minoru Ueki
Shinichi Hara
Minoru Ueki
Shinichi Hara
Application Number:
JP2000087480A
Publication Date:
August 18, 2004
Filing Date:
March 27, 2000
Export Citation:
Assignee:
Hiroshima NEC Corporation
International Classes:
H01L21/00; G11C29/44; H01L21/02; H01L21/66; (IPC1-7): G11C29/00; H01L21/02; H01L21/66
Domestic Patent References:
| JP11161917A | ||||
| JP10233350A | ||||
| JP11045839A | ||||
| JP4123417A |
Attorney, Agent or Firm:
Tadashi Takahashi
Masatake Shiga
Masakazu Aoyama
Yasuhiko Murayama
Masatake Shiga
Masakazu Aoyama
Yasuhiko Murayama