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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPH02168496
Kind Code:
A
Abstract:

PURPOSE: To change bit constitution with an external control signal through the same integrated circuit and optimize the use of a definite memory cell number by making bit number of one word variable with the external control signal so as to switch the function of a RAM and the function of an FIFO.

CONSTITUTION: The presence of a relevant chip, a memory function and a bit number for one word or the like are selected by a chip select signal the inverse of CS, a mode control signal FOM and bit length selection signals m0, m1 from the outside of a semiconductor memory circuit, and an external write designation signal the inverse of WREQ and a readout designation signal the inverse of RREQ or the like are accepted by a chip control circuit 10. An address buffer 12 selects an effective address length of address inputs A0 - A12 in response to the bit function designated by the circuit 10, and when the circuit 10 selects the FIFO mode, an address counter 14 counts each write and readout address. Then the bit constitution of memory cell arrays 16A, 16b being the result of two block divisions is varied in response to the bit constitution designated by the circuit 10 to utilize the memory cell number optimizingly.


Inventors:
ISHII JUICHI
SAKO NORIMITSU
Application Number:
JP3978789A
Publication Date:
June 28, 1990
Filing Date:
February 20, 1989
Export Citation:
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Assignee:
KAWASAKI STEEL CO
International Classes:
G11C11/41; G06F5/10; G11C7/00; G11C7/10; G11C11/401; (IPC1-7): G11C7/00; G11C11/41
Domestic Patent References:
JPS6376185A1988-04-06
JPS58194193A1983-11-12
JPS63257990A1988-10-25
JPS61269288A1986-11-28
Attorney, Agent or Firm:
Satoshi Takaya (2 outside)