PURPOSE: To improve a dynamic response provided by a bipolar transistor and to restore trade-off with the increase of power dispersion.

CONSTITUTION: A column access circuit 20 of a memory cell is provided with a pair of drivers 54 and 56 for energizing bit lines for writing data, the respective drivers are provided with bipolar transistors to be operated by currents and voltages supplied to base terminals by a pair of FET 62 and 64, and one FET 64 excludes the flow of current in non-conducted state by short-circuiting the emitter terminal and base terminal of the transistor 60. This FET is overridden by the other FET 62 for supplying the base current in the conducted state during the write of cells. The other FET performs writing by being energized with a column address signal to the drain terminal and a data input signal to the gate of the FET during the simultaneous generation of these two signals.