Title:
半導体メモリ装置及びビットラインセンシング方法
Document Type and Number:
Japanese Patent JP4146215
Kind Code:
B2
Abstract:
In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.
Inventors:
Lin Keanan
Yanagi Hou
Ginger
Deposition
Yanagi Hou
Ginger
Deposition
Application Number:
JP2002330958A
Publication Date:
September 10, 2008
Filing Date:
November 14, 2002
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G11C11/409; G11C11/4091; G11C7/06; G11C7/12; G11C11/4076
Domestic Patent References:
| JP4370596A | ||||
| JP2000195268A | ||||
| JP2002157885A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro