To provide a semiconductor memory device which incorporates a defective memory cell relieving circuit in which area overhead is small and speed overhead is nonexistent and which has high chip yield and reliability.

A memory cell array constituting of a plurality of memory cells (MC00-MCij) is provided with redundant memory cells (MCOJ+1-MCIJ+1) of one column (sense amplifier + pairs of bit line), and memory cells (MCRA0- MCRAj+1) for storing replacement information of one row, only first one time when a power source is applied to chips, read operation is performed for the memory cell for storing replacement information, data is transferred to a control circuit, a write circuit and a read circuit of a normal memory cell is used for write/read of replacement information, In a Y selection circuit control signals (CS0-CSj) generated by the control circuit based on replacement information (DR0-DRj), data from 0th to a defective column-1st are made 'L' and the other are made 'H', chip area overhead by incorporating a defective memory cell relieving circuit can be reduced, and as an address comparison circuit for replacing defective memory cell is not required,overhead of an access time by address replacement operation is not caused.