PURPOSE: To reduce the area of a transistor forming region required on the surface of a semiconductor substrate by vertically arranging a source region, a channel region and a drain region to the surface of the semiconductor substrate.
CONSTITUTION: An N well 13 is formed to a P-type Si substrate 1, and a high- concentration N+ diffusion region 14 as a diffusion layer for a contact with the N well 13 is shaped. A trench 2 is formed through an RIE method, a capacitance oxide film 4 is grown, and polysilicon is deposited in the trench 2 and a storage node 3 is shaped. A protective oxide film is formed onto the whole surface, a silicon nitride film is shaped in regions except the trench 2, and an oxide film is formed onto the storage node 3 through oxidation. The nitride film and the oxide film on the P-type Si substrate 1 are removed, the lateral- epitaxial growth of Si is conducted, growth is stopped at a certain position, the oxide film 5 exposed onto the storage node 3 is removed to shape an opening section, and lateral-epitaxial growth is performed onto the oxide film 5 with the opening section and the opening section again. The area of a memory cell is determined only by the surface area of the trench 2, thus acquiring the large degree of integration.
OKADA SHOZO
INOUE MICHIHIRO
