To provide a memory system capable of exchanging data held in each of a plurality of buffer parts.

A memory system of an embodiment comprises: a plurality of memory cell transistors provided for each block and capable of holding data; transfer transistors whose drains are connected to word lines connected to control gates of the memory cell transistors, in each of the block; a row decoder containing a voltage adjustment circuit which is connected to gates of the transfer transistors and capable of transferring a desired voltage; a voltage generation circuit for generating a voltage supplied to the transfer transistors; and a control circuit for controlling the row decoder and the voltage generation circuit. In writing data, the gates of transfer transistors in unselected blocks are connected with the voltage adjustment circuit, and the gates of transfer transistors in selected blocks are disconnected from the voltage adjustment circuit.