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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3678331
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which assures higher read operation rate without deteriorating low voltage characteristic, low power consumption property and reduction in size.
SOLUTION: In a semiconductor memory device which functions as a DRAM comprising a memory cell array in which the memory cells 9 are provided in the form of matrix, word lines 7 for connecting the memory cells 9 in the row direction and bit lines 8 for connecting memory cells 9 in the column direction, the power supply voltage switching circuits 1A, 1B, 1C are provided for the sense amplifier drive circuits 4A, 4B, 4C arranged along the direction of bit line 8 in order to switch the power supply voltage of the sense amplifier 5 to the external power supply VDD from the internal voltage drop power supply VINT while the readout data is amplified with the sense amplifier 5 in the selecting operation of the memory cell 9. Thereby, charges are supplied via the sense amplifier drive circuit and the number of sense amplifiers which operate simultaneously can be reduced and thereby data amplifying rate becomes high.


Inventors:
Shunichi Iwanari
Akinori Shibayama
Application Number:
JP31602998A
Publication Date:
August 03, 2005
Filing Date:
November 06, 1998
Export Citation:
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Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C11/41; G11C11/401; G11C11/409; G11C16/06; H01L21/8242; H01L27/108; (IPC1-7): G11C11/409; H01L21/8242; H01L27/108
Domestic Patent References:
JP9204777A
JP9213078A
JP4047585A
JP5062461A
JP200011656A
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama