Title:
半導体メモリ装置
Document Type and Number:
Japanese Patent JP4386312
Kind Code:
B2
Abstract:
The present invention relates to a semi-conductor memory device, comprises global data bus lines and single data strobe lines and reference comparing voltage lines with the number being identical to the number of data being coupled between a bank and an input, output interface circuit part; a clamping means connected every each line for fixing the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines to a regular level of an electric potential; a first to a third driving means connected to every ends of both sides of the numerous global data bus lines and the data strobe lines and the reference comparing voltage lines, for controlling a drive of each lines by a combination of an input, output enable signal and a data output strobe signal and each data signal; a first receiving means connected to ends of both sides of the data strobe lines, for receiving a strobe signal carried on the data strobe lines and comparing it with a reference comparing voltage and thereby outputting the data strobe signal; a second receiving means connected to respective ends of both sides of the numerous global data bus lines, for comparing each data signal with a reference comparing voltage signal and outputting each data value under a control of a data strobe signal being outputted from the first receiving means.
Inventors:
Xu Won Source
Application Number:
JP2000195208A
Publication Date:
December 16, 2009
Filing Date:
June 28, 2000
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/407; G11C7/10; G11C11/401; G11C11/409; G11C11/4093; G11C11/4096
Domestic Patent References:
| JP9231759A | ||||
| JP8138377A | ||||
| JP9106671A | ||||
| JP64010492A | ||||
| JP4132073A |
Attorney, Agent or Firm:
Kyosei International Patent Office