To provide a random number generator suitable for installation inside a semiconductor memory device with simple and small scale circuit configuration by inputting data to be used inside the semiconductor memory device and outputting the parity arithmetic value of those data as random number data.
A random number generation circuit 10 is composed of a parity arithmetic circuit. Based on inputted data, the random number generation circuit 10 outputs the data of '0' or '1' at random. Concretely, address data are received from an address buffer 1, parity arithmetic is performed to these data by the parity arithmetic circuit and as a result, parity output data P are supplied to a data switching circuit 30. The random number generation circuit 10 is usually composed of plural counters or frequency dividers but in this case, since the parity arithmetic circuit is used, the random number can be easily generated in small circuit scale.
KIMURA MASAKAZU
NAKAYAMA TOSHIHIRO
SHIGA TAKANORI
FUJITA YOSHIYUKI
