To provide a semiconductor memory device by which delays in the control signals for control sensing amplifiers can be suppressed effectively without significantly changing the manufacturing steps actually used.

Dummy bit line pairs DBL and/DBL are disposed between desired bit line pairs in a memory cell array 100. Since the dummy bit line pairs DBL and/DBL have no bearing on normal operations, such as reading out of data stored in the memory cell or the like, there is not need to dispose sensing amplifiers SA in a region X in a sensing amplifier array 110 adjacent to the dummy bit line pairs DBL and /DBL. In this way, a vacant region X is formed in the sensing amplifier array 100. The region X has at least a width W, corresponding to the space between the dummy bit line pairs. A contact part C for electrically connecting between a sensing amplifier controlling signal line SLA and a low-resistance sensing amplifier controlling signal line SLB is formed. That is to say, the region X is used as shutting region of the sensing amplifier control signal line.