PURPOSE: To confirm easily the operating state of a spare memory by applying externally a high voltage and inactivating forcibly a spare address decoder so as to perform sequentially read of information to all memory elements and sequential read as to all addresses.
CONSTITUTION: When a high voltage is applied externally via an external terminal 56 of a spare row address decoder, an FET55 is turned on, a node (b) is brought into a low level, an FET33 is turned off and a word line 42 or the like is kept low level. Thus, the spare row address decoder is inactivated forcibly. A spare column address decoder is inactivated forcibly in similar way, and prescribed same information is written in all memory elements in this state and it is read sequentially as to all the addresses and compared with the stored information to confirm easily the operating state of the spare memory such as the addresses used for the spare memory.
| JPS60217596 | SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP3221929 | SEMICONDUCTOR DEVICE |
SHIMOTORI KAZUHIRO
FUJISHIMA KAZUYASU
MIYATAKE HIDEJI
