PURPOSE: To execute low power consumption by installing a word line for plural memory cells each of which stores plural pieces of bit information, and linking this and a block selecting line by the gate circuit controlled by a data line selecting signal.
CONSTITUTION: The linking of large word lines W0, W1... of the block selecting line operating in response to an X address decoder output and word lines WD0, WD1... for eight memory cells MC0WMC7 each which stores bit information, etc., is selectively controlled through FETQ3, Q4... operating in response to selecting signals DS0, DS1... of the data line selected by a Y address decoder output. By such constitution, a wasteful electric current will not flow at the memory cell in which the data line is in a non-selective condition, and the low power consumption can be attained.
SAEKI AKIRA
MINATO OSAMU
SASAKI TOSHIO
SASAKI KATSURO
