Title:
半導体メモリデバイスおよびチップ積層型の半導体デバイス
Document Type and Number:
Japanese Patent JP5310439
Kind Code:
B2
Abstract:
Disclosed here is a semiconductor memory device including: a semiconductor substrate; a plurality of pads formed on the semiconductor substrate and configured to permit data input and output; and a memory core block and an I/O block integrated on the semiconductor substrate. The data items are input and output to and from the plurality of pads at twice a maximum access rate in effect.
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Inventors:
Kuroda Makoto
Application Number:
JP2009217410A
Publication Date:
October 09, 2013
Filing Date:
September 18, 2009
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11C11/407; G11C11/401
Domestic Patent References:
| JP2003308694A | ||||
| JP11191292A | ||||
| JP9297994A |
Attorney, Agent or Firm:
Takahisa Sato
Previous Patent: JPS5310438
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